1. Field of the Invention
Generally, the present disclosure relates to the formation of microstructures, such as advanced integrated circuits, and, more particularly, to the fabrication of conductive structures, such as metal regions, and the monitoring of processes associated therewith.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption. As typically the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these inter-connect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area. The reduced cross-sectional area of the interconnect lines, possibly in combination with an increase of the static power consumption of extremely scaled transistor elements, may require a plurality of stacked metallization layers to meet the requirements in view of a tolerable current density in the metal lines.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.13 μm and even less may, however, require significantly increased current densities in the individual interconnect lines, despite the provision of a relatively large number of metallization layers, owing to the significant number of circuit elements per unit area. Operating the interconnect lines at elevated current densities, however, may entail a plurality of problems related to stress-induced line degradation, which may finally lead to a premature failure of the integrated circuit. One prominent phenomenon in this respect is the current-induced material transportation in metal lines, also referred to as “electromigration,” which may lead to the formation of voids within and hillocks next to the metal line, thereby resulting in reduced performance and reliability or complete failure of the device. For instance, aluminum lines embedded into silicon dioxide and/or silicon nitride are frequently used as metal for metallization layers, wherein, as explained above, advanced integrated circuits having critical dimensions of 0.18 μm or less may require significantly reduced cross-sectional areas of the metal lines and, thus, increased current densities, which may render aluminum less attractive for the formation of metallization layers.
Consequently, aluminum is increasingly being replaced by copper as copper exhibits a significantly lower resistivity and exhibits significant electromigration effects at considerably higher current densities compared to aluminum. The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristic to readily diffuse in silicon dioxide and a plurality of low-k dielectric materials. To provide the necessary adhesion and to avoid the undesired diffusion of copper atoms into sensitive device regions, it is, therefore, usually necessary to provide a barrier layer between the copper and the dielectric material in which the copper lines are embedded. Although silicon nitride is a dielectric material that effectively prevents the diffusion of copper atoms, selecting silicon nitride as an interlayer dielectric material is less then desirable, since silicon nitride exhibits a moderately high permittivity, thereby increasing the parasitic capacitance of neighboring copper lines. Hence, a thin conductive barrier layer that also imparts the required mechanical stability to the copper is formed to separate the bulk copper from the surrounding dielectric material and only a thin silicon nitride or silicon carbide or silicon carbon nitride layer in the form of a capping layer is frequently used in copper-based metallization layers. Currently, tantalum, titanium, tungsten and their compounds, with nitrogen and silicon, tungsten/cobalt/phosphorous compounds, tungsten/cobalt/boron compounds and the like, are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of suppressing diffusion and enhancing adhesion properties.
Another characteristic of copper significantly distinguishing it from aluminum is the fact that copper may not be readily deposited in larger amounts by chemical and physical vapor deposition techniques, in addition to the fact that copper may not be efficiently patterned by anisotropic dry etch processes, thereby requiring a process strategy that is commonly referred to as the damascene or inlaid technique. In the damascene process, first a dielectric layer is formed which is then patterned to include trenches and vias which are subsequently filled with copper or copper alloy, wherein, as previously noted, prior to or after filling in the metal, a conductive barrier layer is formed. The deposition of the bulk copper material into the trenches and vias is usually accomplished by wet chemical deposition processes, such as electroplating and electroless plating, thereby requiring the reliable filling of vias with an aspect ratio of 5 and more with a diameter of 0.1 μm or even less in combination with trenches having a width ranging from 0.1 μm to several μm. Although electrochemical deposition processes for copper are well established in the field of electronic circuit board fabrication, a substantially void-free filling of high aspect ratio vias is an extremely complex and challenging task, wherein the characteristics of the finally obtained copper metal regions significantly depend on process parameters, materials and geometry of the structure of interest. Since the dimensions of interconnect structures are determined by the design requirements and may, therefore, not be significantly altered for a given microstructure, it is of great importance to estimate and control the impact of materials, such as conductive and nonconductive barrier layers, of the copper microstructure and their mutual interaction on the characteristics of the interconnect structure so as to insure both high yield and the required product reliability. In particular, it is important to identify and monitor degradation and failure mechanisms in interconnect structures for various configurations so as to maintain device reliability for every new device generation or technology node.
Accordingly, a great deal of effort has been invested in investigating the characteristics of copper-based metal regions and of the manufacturing techniques associated therewith, in view of electromigration, leakage current behavior and the like, in order to find new materials and process strategies for forming copper-based metallization layers of increased reliability and packing density. Consequently, test structures are usually provided in appropriate locations of the substrate, such as the scribe lanes of the substrate, in order to monitor specific process and material characteristics and/or to determine critical parameters and materials for forming metallization features. One criterion of metallization features, such as vias and metal lines, represents the degree of current leakage between neighboring metal regions, since the leakage current may indicate an insufficient degree of insulation, which may result in reduced device reliability or even complete failure of the device, when occurring in actual device areas of the substrate. For example, via chains may be provided as control monitor structures and may be connected to respective probe pads that allow access to the test structure during an electrical test. For example, a via chain may be connected with two probe pads in order to detect whether or not a current flow is occurring between the two probe pads during an electrical test, wherein the respective via chain may represent a specific characteristic of a process flow and geometric configuration that may be monitored by the dedicated via chain. For other characteristics, that is, other values of process flow parameters, respective via chains are provided. However, with increasing the amount of information that one wants to gain by the leakage test structure, the number of probe pads, which require a moderately high amount of area in the last metallization layer, is required, thereby significantly restricting the utilization of leakage test structures.
Since advanced microstructures, such as fast microprocessors, may require an increased interconnect complexity with dense metal structures at extremely reduced dimensions, there exists a need for enhanced or alternative techniques to examine, monitor and control materials and process technologies involved in the fabrication of complex interconnect structures.
The present disclosure is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.